The present invention relates to semiconductor devices exhibiting reduced capacitance loading and to enabling methodology. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
Interconnection technology is constantly challenged to satisfy the ever increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in submicron regimes has become a limiting factor in fabrication.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9. One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 20(trademark) dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnvale, Calif., Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif., BCB (divinylsiloxane bis-benzocyclobutene) and Silk(trademark) dielectric, an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tintanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein an ILD, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low-k material, is formed over an underlying metal level containing metal features, e.g., Cu or Cu alloy features with a silicon nitride capping layer. A damascene opening, e.g., via hole, trench, or dual damascene opening, is then formed in the ILD. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In attempting to implement Cu interconnects with low-k dielectric materials, particularly porous low-k dielectric materials, problems have been encountered. For example, it found that degradation of the low-k material occurred during deposition of a barrier metal layer prior to filling a damascene opening with Cu. Such degradation typically includes an undesirable increase in the dielectric constant.
There exists a need for methodology enabling the use of low-k dielectric materials, particularly porous low-k dielectric materials, in fabricating high density, multi-level interconnection patterns based on Cu. There exists a particular need for methodology enabling the use of such low-k materials while avoiding their degradation during interconnect fabrication.
An advantage of the present invention is a semiconductor device having interconnect patterns exhibiting reduced parasitic Rxc3x97C time delays employing dielectric materials having a low dielectric constant.
Another advantage of the present invention is a method of manufacturing a semiconductor device having interconnect patterns exhibiting reduced parasitic Rxc3x97C time delays employing dielectric materials having a low dielectric constant.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a dielectric layer having an upper surface over a conductive feature; forming an opening in the dielectric exposing an upper surface of the conductive feature; forming a silicon carbide layer having a silicon surface, lining the opening; depositing a barrier layer on the silicon surface of the silicon carbide layer; and filling the opening with copper (Cu) or a Cu alloy.
Another aspect of the present invention is a semiconductor device comprising: a dielectric layer formed over a conductive feature having an upper surface; an opening in the dielectric layer over the upper surface of the conductive feature; a silicon carbide layer having a silicon surface region lining the opening; a diffusion barrier layer on the silicon surface region of the silicon carbide layer and in contact with the upper surface of the conductive feature; and copper (cu) or a Cu alloy filling the opening.
Embodiments of the present invention include forming a dual damascene opening in low-k dielectric materials, such as porous low-k dielectric materials, depositing the silicon carbide layer with silicon surface lining the opening, on the upper surface of the underlying conductive feature, and on the upper surface of the uppermost dielectric layer. Reverse physical sputtering or sputter etching is then conducted to remove the silicon carbide layer from the upper surface of the uppermost dielectric layer and from the upper surface of the underlying conductive feature. A barrier layer is then deposited, such as a composite comprising a layer of tantalum nitride with a layer of alpha-tantalum thereon. A seedlayer can then be deposited followed by filling the opening, as by electrodedeposition or electrodeless deposition, with Cu. Chemical mechanical polishing (CMP) is then conducted to form a planarized upper surface, followed by deposition of a capping layer, such as silicon carbide or silicon nitride.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded and illustrative in nature, and not as restrictive.